1. Field of the Invention
The present invention relates to a semiconductor device including a plug contact. Here, a xe2x80x9cplug contactxe2x80x9d in this case refers to a state in which an electrical conductor is buried in the inside of a hole or a groove that communicates between an upper portion to be connected and a lower portion to be connected, which portions are spaced apart in an up-and-down direction in a layer structure, so as to establish an electrical connection between the two portions.
Here, the term xe2x80x9cupperxe2x80x9d refers to the side to which the principal surface of the substrate is oriented, and the term xe2x80x9clowerxe2x80x9d refers to its opposite side.
2. Description of the Background Art
In a conventional art, in using a plug contact for connection in the up-and-down direction, a hole (hereafter referred to as xe2x80x9cupper contact holexe2x80x9d) for providing contact from an upper side to a plug contact located on a lower side (hereafter referred to as xe2x80x9clower plugxe2x80x9d) is dug downwards to form an opening. This opening is often represented as xe2x80x9cdropping a contact holexe2x80x9d or xe2x80x9cdropping a contactxe2x80x9d.
If the upper contact hole is dropped to a place out of the lower plug due to pattern deviation or dimension errors, the contact made of an electrical conductor formed in the upper contact hole reaches a lower layer that is not originally intended. If the lower layer is an electrical conductor or the like, a short circuit is generated against the will of the designer, thereby raising a problem.
For this reason, the lower plug on which the upper contact hole is to be dropped is made to have a large diameter while the upper contact hole is made to have a small diameter so that the upper contact hole will always fall on the upper surface of the lower plug even if the position of the upper contact hole is deviated to the maximum.
Referring to FIGS. 10 to 19, a method of producing a semiconductor device according to a prior art technique will be described.
Referring to FIG. 11, an isolation oxide film 2 is formed on a semiconductor substrate 1 made of silicon shown in FIG. 10. Referring to FIG. 12, a transistor 3 is formed. Referring to FIG. 13, a stopper film 4 is formed. Referring to FIG. 14, a portion of the stopper film 4 is left as a side wall 5 on both sides of the transistor 3, and the other portions of the stopper film 4 are removed.
Referring to FIG. 15, a lower interlayer film 6 is formed so as to cover the semiconductor substrate 1, the isolation oxide film 2, and the transistor 3 from the upper side thereof.
A combination of the material qualities of the stopper film 4 and the lower interlayer film 6 is such that the ratio of the etching rate (i.e. selection ratio) of the lower interlayer film 6 to the etching rate of the stopper film 4 is sufficiently large under an etching condition for removing the lower interlayer film 6. Hereafter, the xe2x80x9cselection ratio of A to Bxe2x80x9d, for example, refers to a value which is obtained by dividing the etching rate of A with the etching rate of B. In order to remove A by etching using B as a stopper, it is desired that the xe2x80x9cselection ratio of A to Bxe2x80x9d is large.
As the material quality of the stopper 4, SiON, densely formed SiO2, and others may be mentioned as examples. As the material quality of the lower interlayer film 6, phosphorus-containing SiO2, coarsely formed SiO2, and others may be mentioned as examples. As the phosphorus-containing SiO2, BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate), PSG (Phospho Silicate Glass), and others may be mentioned as examples. Further, in order to make a coarse SiO2, PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) may be formed, for example.
Referring to FIG. 16, a lower contact hole 7 is opened which is a hole for forming a lower plug. In the etching process for forming this opening, the side wall 5 functions as a stopper film to protect the transistor 3. The semiconductor substrate 1 is exposed on the bottom surface of the lower contact hole 7. After a polycrystal silicon layer is formed on the entire surface from the upper side by thermal CVD (Chemical Vapor Deposition) or the like, unnecessary portions of the polycrystal silicon are removed by CMP (Chemical Mechanical Polishing) or the like so that the polycrystal silicon will remain only in the inside of the lower contact hole 7. Thus, a structure is obtained in which the inside of the lower contact hole 7 is filled with the electrically conductive polycrystal silicon, as shown in FIG. 17, and this polycrystal silicon part forms the lower plug 8. Referring to FIG. 18, an upper interlayer film 9 is formed on the upper side so as to cover the lower interlayer film 6 and the lower plug 8. As the material quality of the upper interlayer film 9, a general insulating film can be used; however, in particular, SiO2, BPTEOS, P-TEOS, SiON, and others may be mentioned as examples.
Referring to FIG. 19, an upper contact hole 10 is formed by digging the upper interlayer film 9 downwards to penetrate therethrough by etching. The lower plug 8 has a larger diameter than the upper contact hole 10, and is disposed so that the lower plug 8 can receive the upper contact hole 10 even if the position of dropping the upper contact hole 10 is deviated to some extent.
As described above, in the prior art, in order to prevent short circuits, the lower plug is formed to have a large diameter while the upper contact hole is formed to have a small diameter. However, this raises a problem that, by forming the upper contact hole to have a small diameter, the contact resistance increases. Furthermore, it raises a problem that, by forming the lower plug to have a large diameter, the size of the semiconductor device increases.
Therefore, an object of the present invention is to provide a semiconductor device and a production method thereof in which the upper contact hole can be formed to have a larger diameter without the need for enlarging the lower plug.
In order to achieve the above-mentioned object, a semiconductor device according to the present invention includes a semiconductor substrate, a lower interlayer film formed on an upper side of the semiconductor substrate, an intermediate film formed on an upper side of the lower interlayer film, an upper interlayer film formed on an upper side of the intermediate film, and a lower plug made of an electrically conductive material that penetrates through the lower interlayer film and the intermediate film, wherein the upper interlayer film has an upper contact hole for electrical connection to the lower plug, and the intermediate film has such a material quality that a ratio of an etching rate of the intermediate film to an etching rate of the upper interlayer film is sufficiently small to allow processing of the upper contact hole by etching the upper interlayer film using the intermediate film as a stopper under an etching condition for forming the upper contact hole.
Adoption of the above-mentioned construction prevents the upper contact hole from being connected to the semiconductor substrate or the like located below to generate a short circuit owing to the intermediate film functioning as a stopper even if a region to become the bottom surface of the upper contact hole is deviated from the upper surface of the lower plug or goes out of the upper surface of the lower plug in forming the upper contact hole. Therefore, a semiconductor is provided in which the contact resistance is reduced by forming the upper contact hole to have a larger diameter without the need for enlarging the lower plug.
In the above-mentioned invention, the semiconductor device preferably includes a semiconductor element having a side wall on an upper side of the semiconductor substrate, and the intermediate film preferably has the same material quality as the side wall. Adoption of this construction enables use of the same source material and equipment in the step of forming the side wall and in the step of forming the intermediate film, whereby the semiconductor device can be produced with simpler production equipment.
In the above-mentioned invention, the upper interlayer film preferably has the same material quality as the lower interlayer film. Adoption of this construction enables use of the same source material and equipment in the step of forming the side wall and in the step of forming the intermediate film, whereby the semiconductor device can be produced with simpler production equipment.
In the above-mentioned invention, the lower plug preferably has a shape of being tapered towards a lower side, and a portion that penetrates through the intermediate film is preferably nearer to a parallel shape than a portion that penetrates through the lower interlayer film. Adoption of this construction prevents the upper surface of the lower plug from being enlarged even if the side wall of the lower plug has a moderate slope. Therefore, short circuits between the lower plugs are prevented.
In the above-mentioned invention, the intermediate film preferably has a material quality having a slower etching rate than the lower interlayer film under a wet etching condition for removing the lower interlayer film. Adoption of this construction can easily prevent the upper surface of the lower plug from being enlarged, because the hole formed in the intermediate film is not widened even if the bottom surface area of the lower plug is increased by isotropic etching so as to reduce the electric resistance value.
Further, in order to achieve the above-mentioned object, a method of producing a semiconductor device according to the present invention includes an intermediate film forming step for forming an intermediate film on an upper side of a lower interlayer film which is formed on an upper side of a semiconductor substrate, a plug hole forming step for forming a plug hole which is a hole for forming a lower plug so as to penetrate through the intermediate film and the lower interlayer film, a plug burying step for burying an electrical conductor in an inside of the plug hole to form the lower plug, an upper interlayer film forming step for forming an upper interlayer film on an upper side of the intermediate film and the lower plug so as to cover these, and an upper contact hole forming step for forming an upper contact hole that exposes at least a part of a surface of the lower plug without exposing the lower interlayer film by etching the upper interlayer film using the intermediate film as a stopper, wherein the intermediate film has such a material quality that a ratio of an etching rate of the intermediate film to an etching rate of the upper interlayer film is sufficiently small to allow processing of the upper contact hole by etching the upper interlayer film using the intermediate film as a stopper under an etching condition used in the upper contact hole forming step.
Adoption of the above-mentioned method prevents the upper contact hole from being connected to the semiconductor substrate or the like located below to generate a short circuit owing to the intermediate film functioning as a stopper even if a region to become the bottom surface of the upper contact hole is deviated from the upper surface of the lower plug or goes out of the upper surface of the lower plug in forming the upper contact hole. Therefore, a semiconductor can be produced in which the contact resistance is reduced by forming the upper contact hole to have a larger diameter without the need for enlarging the lower plug.
In the above-mentioned invention, a semiconductor element having a side wall is preferably formed on an upper side of the semiconductor substrate, and the intermediate film is preferably formed to have the same material quality as the side wall in the intermediate film forming step. Adoption of this method enables use of the same source material and equipment in the step of forming the side wall and in the step of forming the intermediate film, whereby the semiconductor device can be produced with simpler production equipment.
In the above-mentioned invention, the upper interlayer film is preferably formed to have the same material quality as the lower interlayer film in the upper interlayer film forming step. Adoption of this method enables use of the same source material and equipment in the step of forming the side wall and in the step of forming the intermediate film, whereby the semiconductor device can be produced with simpler production equipment.
In the above-mentioned invention, the plug hole is preferably formed to have a shape of being tapered towards a lower side in the plug hole forming step so that a portion that penetrates through the intermediate film is nearer to a parallel shape than a portion that penetrates through the lower interlayer film. Adoption of this method prevents the upper surface of the lower plug from being enlarged even if the side wall of the lower plug has a moderate slope. Therefore, short circuits between the lower plugs are prevented.
In the above-mentioned invention, the intermediate film is preferably formed in the intermediate film forming step to have a material quality having a slower etching rate than the lower interlayer film under an etching condition for forming the plug hole in the lower interlayer film. Adoption of this method can easily prevent the upper surface of the lower plug from being enlarged, because the hole formed in the intermediate film is not widened even if the bottom surface area of the lower plug is increased by isotropic etching so as to reduce the electric resistance value.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.